1. Field of the Invention
The present invention relates to a semiconductor device having MOS transistors in which an N-MOS transistor is used as an ESD protection element and whose element isolation structure includes shallow trench isolation.
2. Description of the Related Art
In a semiconductor device including MOS transistors, it is a well known practice to install an “off” transistor, which is an N-MOS transistor whose gate electric potential is fixed to a ground voltage (Vss) to keep in an off state, as an ESD protection element for preventing the breakdown of an internal circuit due to static electricity from an external connection PAD.
The off transistor is usually designed to have a wide transistor width W of the order of several hundreds microns because, unlike other MOS transistors that constitute internal circuits such as a logic circuit, the off transistor needs to permit a sudden flow of a large amount of current caused by the static electricity.
Since the off transistor, although kept in an off state by fixing the gate potential to Vss, has a threshold of 1 V or less as N-MOS transistors of internal circuits have, a certain amount of sub-threshold current generates. A wide width W of the off transistor as mentioned above causes a large off-leak current during the standby period, posing a problem by increasing the overall standby current consumption of an IC to which the off transistor is mounted.
In a semiconductor device using shallow trench isolation as an element isolation structure, in particular, regions prone to cause leak current, such as a crystal defect layer, are found in the vicinity of a shallow trench due to the isolation structure itself or a fabrication method of the isolation structure, thereby making the off leak current of the off transistor an even greater problem.
An improvement for reducing the leak current of the protection element has been proposed in which a plurality of transistors are arranged between a power supply (Vdd) and a ground (Vss) such that the transistors are completely turned off (see JP 2002-231886 A, for example).
However, reducing the width W in order to keep the off leak current of the off transistor small renders the off transistor incapable of implementing its protection function satisfactorily. The proposed remedy also has a problem of an increase in cost for the semiconductor device because of the significant increase in the occupation area by the plurality of transistors arranged between a power supply line (Vdd) and a ground line (Vss) to turn off the transistors completely.